1. Field of the Invention
The disclosed embodiments of the present invention relates to a flip-flop circuit design, and more particularly, to a flip-flop circuit with a circuit structure similar to a true single phase clock (TSPC) structure and having a set/reset function.
2. Description of the Prior Art
In a high-speed phase-locked loop (PLL) circuit, the frequency divider would perform frequency division operation on high-frequency (e.g., above 1 GHz) signals. However, if advanced manufacture processes are unavailable, it is not feasible for a flip-flop used in the frequency divider to be realized by a standard D-type flip-flop element.
In order to solve the above-mentioned problem, the frequency divider may be realized by using a TSPC flip-flop. The TSPC flip-flop may be used in a high-speed circuit. However, the TSPC flip-flop is only allowed to use a single-phase trigger clock in order to avoid clock signals with different phases from concurrently pulling internal data to a high electric potential and a low electric potential, and thus fails to have a set/reset function.
In addition, in a spread spectrum clock (SSC) PLL circuit that may mitigate an electromagnetic interference (EMI), a divisor of the frequency divider has to constantly change in order to spread the spectrum, and the larger is the divisor of the frequency divider, the better the effect of the spread spectrum is. Therefore, how to design a frequency divider that may be employed in high-speed operations as well as a flip-flop circuit having a set/reset function is an important issue.